In-Band Signaling Within Wireless Power Transfer Systems

ABSTRACT

Systems and methods for in-band communication across a wireless power interface from a load device to a source device. The load device selectively modifies the timing of switches within a voltage rectifier coupled to an output of a receive coil within the load device that receives power from a transmit coil within the source device. The source device detects changes in the power transfer (or in the relative timing of a voltage or a current) as digital information received from the load device.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. patent application Ser. No.15/152,444, filed May 11, 2016, which claims the benefit under 35 U.S.C.§119(e) of U.S. Provisional Patent Application No. 62/233,798, filedSep. 28, 2015, and to U.S. Provisional Patent Application No.62/255,072, filed Nov. 13, 2015, the disclosures of which are herebyincorporated herein in their entirety.

FIELD

Embodiments described herein relate to wireless power transfer systems,and more particularly, to in-band signaling across wireless powertransfer systems.

BACKGROUND

An electronic device can receive power from a wireless powertransmitter. In one example, a power transmitter circulates a varyingcurrent through an electromagnetic coil to induce a voltage across theterminals of a magnetically coupled corresponding coil within anelectronic device, thereby inducing a current useful to the electronicdevice inversely proportional to the impedance of the device at thattime. In a typical example, the electronic device directs the inducedcurrent to a circuit configured to recharge a battery or power a load.

Some conventional electronic devices send data back to the powertransmitter by selectively changing their effective impedance; changesin the operating point are monitored by the wireless power transmitterto recover the data. However, the rate at which data can be sent in thismanner is low.

SUMMARY

Many embodiments described herein generally reference systems andmethods for in-band signaling from a load device to a source device of awireless power transfer system. The wireless power transfer system canbe modeled as an air gap transformer; the source device includes aprimary coil and the load device includes a secondary coil. The primarycoil and the secondary coil are magnetically coupled such that when analternating current is applied to the primary coil, an alternatingvoltage is induced across the terminals of the secondary coil.

The induced voltage may be rectified by a synchronous rectifier withinthe load device. To communicate with the source device, the load deviceselectively modifies the timing of one or more switches of thesynchronous rectifier during transitions between half-cycles of thealternating voltage, thereby causing a reduction in the received powerin the load device (e.g., power is reflected from the load device to thesource device).

The source device detects the reflected power from the load and records,caches, and/or buffers the presence of the detected reflected signal asdigital information. Alternatively, should the source device detect theabsence of any reflected power, the source device records the absence ofa reduction in power transfer as a complementary digital bit. The sourcedevice records, caches, and/or buffers recorded bits until a symbol,instruction, header, or other data is received.

BRIEF DESCRIPTION OF THE FIGURES

Reference will now be made to representative embodiments illustrated inthe accompanying figures. It should be understood that the followingdescriptions are not intended to limit the disclosure to a limited setof preferred embodiments. To the contrary, it is intended that thefollowing description covers alternatives, modifications, andequivalents as may be included within the spirit and scope of thedescribed or depicted embodiments and as defined by the appended claims.

FIG. 1 depicts a load device and a source device of a wireless powertransfer system.

FIG. 2 depicts a simplified schematic diagram of a wireless powertransfer system configured for in-band signaling.

FIG. 3A is a waveform representation of current and voltage of a primarycoil of the wireless power transfer system depicted in FIG. 2.

FIG. 3B is a waveform representation of current and voltage of asecondary coil of the wireless power transfer system depicted in FIG. 2.

FIG. 4A is a waveform representation of current and voltage of arectifying switch coupled to the secondary coil of the wireless powertransfer system depicted in FIG. 2, particularly illustratingsuppression of a trailing-edge voltage spike.

FIG. 4B is a timing diagram depicting gate voltage control of atransistor associated with FIG. 4A.

FIG. 5A is a waveform representation of current and voltage associatedwith a primary coil of the wireless power transfer system of FIG. 2,particularly illustrating a current reversal corresponding to thesuppression of the trailing-edge voltage spike depicted in FIG. 4A.

FIG. 5B is a timing diagram illustrating detection of the currentreversal depicted in FIG. 5A.

FIG. 6A is a waveform representation of voltage output from thesynchronous rectifier of FIG. 2, illustrating in-band signaling viatrailing-edge voltage spike suppression.

FIG. 6B is a timing diagram illustrating detection of current reversalscorresponding to the trailing-edge voltage spike suppression depicted inFIG. 6A.

FIG. 7A is a simplified system diagram of a load device of a wirelesspower transfer system facilitating in-band signaling.

FIG. 7B is a simplified system diagram of a source device of a wirelesspower transfer system facilitating in-band signaling.

FIG. 8 depicts operations of a method of in-band signaling from a loaddevice to a source device of a wireless power transfer system.

FIG. 9 depicts operations of a method of demodulating an in-band signalfrom a load device to a source device of a wireless power transfersystem.

FIG. 10 depicts operations of another method of demodulating an in-bandsignal from a load device to a source device of a wireless powertransfer system.

FIG. 11 depicts operations of another method of demodulating an in-bandsignal from a load device to a source device of a wireless powertransfer system.

FIG. 12 depicts operations of a method of adjusting the data transferrate of in-band signaling from a load device to a source device of awireless power transfer system.

The use of the same or similar reference numerals in different figuresindicates similar, related, or identical items.

The use of cross-hatching or shading in the accompanying figures isgenerally provided to clarify the boundaries between adjacent elementsand also to facilitate legibility of the figures. Accordingly, neitherthe presence nor the absence of cross-hatching or shading conveys orindicates any preference or requirement for particular materials,material properties, element proportions, element dimensions,commonalities of similarly illustrated elements, or any othercharacteristic, attribute, or property for any element illustrated inthe accompanying figures.

Additionally, it should be understood that the proportions anddimensions (either relative or absolute) of the various features andelements (and collections and groupings thereof) and the boundaries,separations, and positional relationships presented therebetween, areprovided in the accompanying figures merely to facilitate anunderstanding of the various embodiments described herein and,accordingly, may not necessarily be presented or illustrated to scale,and are not intended to indicate any preference or requirement for anillustrated embodiment to the exclusion of embodiments described withreference thereto.

DETAILED DESCRIPTION

Embodiments described herein generally reference systems and methods forin-band signaling from a load device to a source device of a wirelesspower transfer system. In one example, a wireless power transfer systemsuch as described herein can be an electromagnetic inductive powertransfer system, operating at a selected frequency (herein, the“operational frequency” of the wireless power transfer system) in anon-resonant mode or a resonant mode.

In many embodiments, digital information is transferrable from the loaddevice to the source device via in-band signaling at a baud rateequivalent to, or a multiple or factor of, the operational frequency ofthe wireless power transfer system. In these embodiments, the loaddevice selectively modifies the timing of (e.g., delays) the turn-off ofone or more switches of a synchronous rectifier during a transition froma positive current half-cycle to a negative current half-cycle, therebycausing current to reverse, leading to a momentary reduction in thepower transferred from the source device to the load device.

The source device detects said current reversal (and correspondingreflected power) and records the presence of the current reversal as adigital bit. Alternatively, should the source device detect the absenceof any negative current, the source device records the absence of acurrent reversal as a complementary digital bit. The source device canuse, collect, store, forward, or ignore received bits in any number ofsuitable ways. In one embodiment, the source device buffers recordedbits until a symbol, instruction, header, checksum, an end-of-messageindication, or other data is received. Thus, by selectivelydesynchronizing the rectification circuit (by means of delaying theturn-off) on a per half-cycle basis, the load device communicatesdigital information to the source device.

In-band signaling such as described herein is substantially independentof the load conditions (e.g., impedance) of the load device because thepresence or absence of a current reversal occurs during transitionsbetween half-cycles of the fluctuating magnetic field used by the sourcedevice to convey power to the load device.

For many embodiments described herein, the presence or absence of thecurrent reversal is recorded as a binary bit (e.g., present or notpresent), however such a configuration is not required of allembodiments. For example, the delayed turn-off of the synchronousrectifier switch(es) can affect a phase shift in the current through thesource device; the source device can monitor for such a phase shift andrecord the phase shift as a binary bit. In other cases, the sourcedevice can monitor the magnitude of the reduction in the powertransferred between the source device and the load device (e.g., currentmonitoring, voltage monitoring, phase shift monitoring, and so on) andcan quantize the same into one or more non-binary values.

These and other embodiments are discussed below with reference to FIGS.1-12. However, those skilled in the art will readily appreciate that thedetailed description given herein with respect to these Figures is forexplanatory purposes only and should not be construed as limiting.

Referring now to FIG. 1, there is shown a wireless power transfer systemincluding a load device and a source device in an unmated configuration.The illustrated embodiment depicts a source device 102 that isconfigured to wirelessly transfer energy to a load device 104.

In many examples, the load device 104 may include a processor coupledwith, or in communication with a memory, one or more communicationinterfaces, output devices such as displays and speakers, one or moresensors, such as biometric and imaging sensors, and input devices suchas one or more buttons, one or more dials, a microphone, and/or force ortouch sensing device. The communication interface(s) can provideelectronic communications between the communications device and anyexternal communication network, device or platform, such as but notlimited to wireless interfaces, Bluetooth interfaces, Near FieldCommunication interfaces, infrared interfaces, USB interfaces, Wi-Fiinterfaces, TCP/IP interfaces, network communications interfaces, or anyconventional communication interfaces.

Although the load device 104 illustrated in FIG. 1 depicts a wristwatchor smart watch, any electronic device may be suitable to receive energyfrom the source device 102. For example, a suitable electronic devicemay be any portable or semi-portable electronic device that may receiveenergy inductively (herein, generally, a “load device”), and a suitabletransmitting device may be any portable or semi-portable docking stationor charging device that may transmit energy inductively (herein,generally, a “source device”). Example electronic devices include, butare not limited to, a telephone, a gaming device, a wearable device, adigital music player, a tablet computing device, a laptop computingdevice, and other types of portable and consumer electronic devices thatare configured to transmit and/or receive energy inductively.

The source device 102 and the load device 104 may each respectivelyinclude a housing to enclose, support, and carry electronic, mechanicaland structural components therein. In many examples, and as depicted,the load device 104 may have a larger lateral cross section than that ofthe source device 102, although such a configuration is not required. Inother examples, the source device 102 may have a larger lateral crosssection than that of the load device 104. In still further examples, thecross sections may be substantially the same. And in other embodiments,the source device can be adapted to be inserted into a charging port inthe load device.

The source device 102 may be connected to a power source by cord orconnector. For example, the source device 102 can receive power from awall outlet, or from another electronic device through a connector, suchas a USB connector. Additionally or alternatively, the source device 102may be battery operated. Similarly, although the illustrated embodimentis shown with the connector coupled to the housing of the source device102, the connector may be connected by any suitable means. For example,the connector may be removable and may include a connector that is sizedto fit within an aperture or receptacle opened within the housing 106 ofthe source device 102.

The load device 104 may include a bottom surface that may interfacewith, align or otherwise contact a top surface of the source device 102.In this manner, the load device 104 and the source device 102 may bepositionable with respect to each other. In certain embodiments, the topsurface of the source device 102 may be configured in a particular shapethat mates with a complementary shape of the load device 104. Theillustrative top surface may include a concave shape that follows aselected curve. The bottom surface of the load device 104 may include aconvex shape following the same or substantially similar curve as thetop surface.

In other embodiments, the surfaces can have any given shape anddimension. For example, the surfaces may be substantially flat.Additionally or alternatively, the source and load devices 102, 104 canbe positioned with respect to each other using one or more alignmentmechanisms. As one example, one or more magnetic devices may be includedin the source and/or load devices and used to align the source and loaddevices. In another example, one or more actuators in the source and/orload devices can be used to align the source and load devices. And inyet another example, alignment features, such as protrusions andcorresponding indentations in the housings of the source and loaddevices, may be used to align the source and load devices. The design orconfiguration of the surfaces, one or more alignment mechanisms, and oneor more alignment features can be used individually or in variouscombinations thereof.

FIG. 2 depicts a simplified schematic diagram of a wireless powertransfer system configured for in-band signaling. The schematicillustrated may represent a wireless power transfer system such as shownin FIG. 1. The wireless power transfer system 200 includes a sourcedevice 202 for transmitting power and a load device 204 for receivingpower, illustrated as coupled by two electrically-isolated halves of anair-gap transformer.

Initially, reference is made to the circuit topology of the illustratedexample embodiment. It is appreciated that the particular illustratedembodiment and schematic diagram is merely an example; other circuittopologies including a greater number or a fewer number of elementsand/or connections between elements is possible.

The source device 202 includes a processor 206 and a power supply 208.The processor 206 may be implemented as any electronic device orcombination of electronic devices capable of processing, receiving, ortransmitting data or instructions. For example, the processor 206 mayinclude one or more of a microprocessor, a central processing unit, anapplication-specific integrated circuit, a digital signal processor, avoltage or current comparator circuit, a phase comparator circuit, ananalog circuit, or any other combinations of such devices. As describedherein, the term “processor” is meant to encompass a single processor orprocessing unit, multiple processors, multiple processing units, orother suitably configured computing element(s).The power supply 208 canbe an internal or external power source.

The processor 206 is configured to control an inverter 210 that iscoupled to the output of the power supply 208. The inverter 210 convertsthe direct current output from the power supply 208 into an alternatingcurrent. The processor 206 controls the frequency at which the inverter210 alternates the current and the timing of the operation of switchesassociated with the inverter 210, such as the inverter switches 212 a,212 b, 212 c, and 212 d.

The inverter 210 can be formed as any suitable type of a direct currentto alternating current converter. The inverter 210 can outputalternating current in any suitable manner, such as a square wave, asine wave, or any other alternating current waveform. One examplewaveform output from the inverter 210 is shown in FIG. 3A, depictingcurrent and voltage measured across the output of the inverter 210 ofthe wireless power transfer system of FIG. 2. Depicted are two periodsof alternating current: a positive half-cycle 300, a negative half-cycle302, a second positive half-cycle 304, and a second negative half-cycle306. The voltage output from the inverter 210 in the depicted waveformis substantially similar to a square wave; deformations in thesubstantially square waveform depicted represent losses introduced bythe inverter 210.

The inverter 210 can be constructed as an H-bridge. In this example, theinverter 210 is formed from four transistors (or, more generally,switches) arranged in pairs of two, identified in the illustratedembodiment as the inverter switches 212 a, 212 b, 212 c, and 212 d. Thefirst pair includes inverter switches 212 a and 212 d and the secondpair includes inverter switches 212 b and 212 c. The pairs of switchesdefine two separate and inverse electrical paths between the powersupply 208 and an electromagnetic coil, identified as the primary coil216. The processor 206 alternates which electrical path couples thepower supply 208 to the primary coil 216. In many examples, theprocessor 206 alternates the power to the primary coil 216 at afrequency selected so that the primary coil 216 and the associatedcapacitors 218 resonate.

In some embodiments, the inverter switches 212 a, 212 b, 212 c, and 212d can each be associated with an inverter diode, respectively labeled asthe inverter diodes 214 a, 214 b, 214 c, and 214 d. The inverter diodes214 a, 214 b, 214 c, and 214 d are placed across the respective sourceand drain of the inverter switches 212 a, 212 b, 212 c, and 212 d suchthat one inverter diode is associated with each inverter switch. In someembodiments, the inverter diodes 214 a, 214 b, 214 c, and 214 d can bediscrete and separate elements from the inverter switches, although thisis not required. For example, in one embodiment the inverter diodes 214a, 214 b, 214 c, and 214 d are implemented as body diodes within theinverter switches. In other examples, the inverter diodes can beimplemented as external diodes, such as Schottky diodes. The inverterdiodes 214 a, 214 b, 214 c, and 214 d of the inverter switches 212 a,212 b, 212 c, and 212 d can be used as supplemental current paths duringthe operation of the inverter 210. More specifically, in certainembodiments, the inverter 210 may briefly pause between switchingbetween the two separate and inverse electrical paths. This “dead time”between inverter cycles may be included in order to prevent“shoot-through” current which may occur if the inverter switches 212 a,212 c (or, respectively, the inverter switches 212 b, 212 d) are in theon-state at the same time. In other words, the shoot-through conditionmay occur if the turn-off of the active switch pair is slower than theturn-on of the active switch pair of the next inverter cycle, therebyeffectively shorting the power supply 208 for a brief period of time.During the dead time between inverter cycles, current within the primarycoil 216 may be conducted through one or more of the inverter diodes 214a, 214 b, 214 c, and 214 d, thereby preventing said current from causingdamage to one or more of the inverter switches 212 a, 212 b, 212 c, and212 d during the dead time period. As may be appreciated, the voltageacross an inverter diode may increase rapidly when said diode beginsconducting current during a dead time period. The forward voltage of theconducting diodes may be observed as a voltage spike when measuredacross the primary coil 216, for example as shown in FIG. 3A.

The load device 204 includes a processor 220 and a variable load 222. Aswith the processor of the source device 202, the processor 220 may beimplemented as any electronic device or combination of electronicdevices capable of processing, receiving, or transmitting data orinstructions. For example, the processor 220 may include one or more ofa microprocessor, a central processing unit, an application-specificintegrated circuit, a digital signal processor, an analog circuit, orany other combinations of such devices.

The variable load 222 can be any circuit or network of circuits withinthe load device 204 that require direct current to operate. For example,the variable load 222 may include one or more communication interfaces,output devices such as displays and speakers, one or more sensors, suchas biometric and imaging sensors, one or more batteries, and inputdevices such as one or more buttons, one or more dials, a microphone,and/or force or touch sensing device.

The processor 220 is configured to control a synchronous rectifier 224that is coupled to the terminals of an electromagnetic coil, identifiedas the secondary coil 226. The synchronous rectifier 224 convertsalternating induced in the secondary coil 226 into a direct currentuseful to the load device 204. The processor 220 controls the switchesof the synchronous rectifier 224. Typically, the synchronous rectifier224 operates at the resonance frequency of the primary coil 216 and theassociated capacitors 218. The output of the synchronous rectifier canbe coupled to an output capacitor 232 which serves as a low-pass filter.The output capacitor 232 filters out high frequency components of theoutput of the synchronous rectifier into a direct-current voltage usefulto the variable load 222.

The synchronous rectifier 224 is formed from four transistors (or, moregenerally, switches) arranged in pairs of two, identified as therectifier switches 228 a, 228 b, 228 c, and 228 d. The first pairincludes rectifier switches 228 a and 228 c and the second pair includesrectifier switches 228 b and 228 d. The pairs of switches define twoseparate and inverse electrical paths between the secondary coil 226 andthe variable load 222. The processor 220 alternates which electricalpath couples the secondary coil 226 to the variable load 222.

In some embodiments, the synchronous rectifier 224 includes fourrectifying diodes 230 a, 230 b, 230 c, and 230 d. The rectifying diodes230 a, 230 b, 230 c, and 230 d are placed across the respective sourceand drain of the rectifier switches 228 a, 228 b, 228 c, and 228 d suchthat the rectifying diode 230 a is coupled the source and drain of therectifier switch 228 a, the rectifying diode 230 b is coupled the sourceand drain of the rectifier switch 228 b, and so on. In some embodiments,the rectifying diodes can be discrete and separate elements from therectifier switches, although this is not required. For example, in manyembodiments the rectifying diodes are implemented as body diodes withinthe rectifier switches. In other embodiments, the rectifying diodes maybe implemented with separate diodes, such as Schottky diodes. In someembodiments, the rectifying diodes are used in lieu of the synchronousrectifier switches until the load device 204 is capable to provide avoltage sufficient to switch the rectifying switches (e.g., when theload device 204 is in a low-power mode). In another non-limitingphrasing, the rectifying diodes can be used as an asynchronousrectifier.

Next, reference is made to the operation of transferring power from thesource device to the load device of the example embodiment illustratedin FIG. 2. As noted above, it is appreciated that the operation of theparticular illustrated embodiment and schematic diagram is a generalizedand simplified to facilitate an understanding of the various embodimentsdescribed herein; other circuit topologies can operate in a differentmanner than that described below.

In operation, the source device 202 circulates a time-varying currentthrough the primary coil 216 that generates a time-varying magnetic fluxin response. The secondary coil 226, within the load device 204, isplaced nearby the source device 202 so that the primary coil 216 and thesecondary coil 226 are magnetically coupled. In this manner, thetime-varying magnetic flux generated by the primary coil 216 induces analternating voltage across the terminals of the secondary coil 226resulting in an alternating current through operational components ofthe load device 204 related to the impedance of the variable load 222.

As noted above, the synchronous rectifier 224 includes four transistors(or, more generally, switches) arranged as pairs of two. One pair ofswitches, including the rectifier switches 228 a and 228 c, define anelectrical path between the positive terminal of the secondary coil 226and a positive voltage input terminal of the variable load 222 when thealternating voltage across the secondary coil 226 is positive, whichoccurs for one half of each period of the alternating voltage (herein,the “positive half-cycle”). During the positive half-cycle, currentcirculates from the positive terminal of the secondary coil 226, throughthe variable load 222 and the output capacitor 232, to the negativeterminal of the secondary coil 226.

The synchronous rectifier 224 also includes a second pair of switches,the rectifier switches 228 b and 228 d, that define an electrical pathbetween the negative terminal of the secondary coil 226 and the positivevoltage input terminal of the variable load 222 when the alternatingvoltage across the secondary coil 226 is negative, which, like thepositive half-cycle, occurs for one half of each period of thealternating voltage (herein, the “negative half-cycle”). During thenegative half-cycle, current circulates from the negative terminal ofthe secondary coil 226, through operational components of the loaddevice 204, to the positive terminal of the secondary coil 226.

In operation, the processor 220 of the load device 204 activates therectifier switches 228 a and 228 c for each positive half-cycle (herein,the “positive half-cycle pair” of switches) and the rectifier switches228 b and 228 d for each negative half-cycle (herein, the “negativehalf-cycle pair” of switches). In this manner, alternating voltage isrectified to a positive voltage V_(out) and alternating current isrectified and (optionally) filtered by the output capacitor 232 toprovide direct current useful to operate the variable load 222.

In operation, the voltage across the rectifying diodes 230 a, 230 b, 230c, and 230 d can be used by the processor 220 as a trigger to activatethe switches of a particular half-cycle pair. In this manner, thesynchronous rectifier 224 remains closely synchronized to the frequencyand phase of the alternating voltage induced across the terminals of thesecondary coil 226.

More specifically, when the induced current in the secondary coil 226changes from negative to positive, the rectifying diodes 230 a and 230 cconduct to carry the current at the start of the positive half-cycle.The forward voltage across the rectifying diodes 230 a and/or 230 c canbe sensed and used as a trigger to activate the rectifier switches 228 aand 228 c. After the synchronous rectifier switches are turned on, theassociated rectifying diodes no longer carry current (e.g.,substantially all current flows through the switch instead). In thismanner, controlling the time at which the rectifier switches turn oncontrols whether voltage across the secondary coil 226 spikes (e.g.,rapidly increases) at the initial part of the positive half cycle. Theamplitude of this voltage spike is the forward voltage of the rectifierdiode and the width is the delay from detection of the diode forwardvoltage to the activation of the corresponding rectifier switch (see,e.g., FIG. 3B). A similar voltage spike can be observed on the otherside of the secondary coil 226 across the source and drain of therectifier switch 228 c.

Similarly, as the voltage of a negative half-cycle exceeds the thresholdvoltage of the rectifying diodes 230 b and 230 d, said diodes beginconducting current, resulting in a rapid increase in voltage across therectifier switches 228 b and 228 d. In other words, voltage measuredacross the source and drain of the rectifying switch 228 b spikes duringthe initial part of a negative half-cycle as a result of current flowingthrough the rectifying diode 230 b. As the induced current in thesecondary coil 226 changes from positive to negative the rectifyingdiodes 230 b and 230 d conduct to carry the current at the start of thenegative half-cycle. The forward voltage across the rectifying diodes230 b or 230 d can be sensed and used as a trigger to activate therectifier switches 228 b and 228 d. A voltage spike may be seen at theinitial part of the negative half cycle during the time that therectifying diodes 230 b and 230 d are conducting current. A similarvoltage spike can be measured across the source and drain of therectifying switch 228 d.

These voltage spikes are generally referred to herein as “leading edgespikes” of the voltage measured across either (or both) of the twoswitches of a half-cycle pair. The processor 220 monitors for theleading edge spike and upon detecting the same, activates the respectivehalf-cycle transistor pair to direct the current associated with thathalf-cycle to the variable load 222.

Once a half-cycle pair is activated by the processor 220, voltage acrossthe diodes settles back to the root mean-squared voltage output from thesynchronous rectifier 224, identified in the schematic diagram asV_(out).

Near the end of a half-cycle (e.g., approaching a transition between apositive half-cycle and a negative half-cycle, detected by currentmonitoring, voltage monitoring, phase synchronization, or any othersuitable process), the processor 220 disables the switches associatedwith the then-active half-cycle pair. Provided that the switch isdisabled prior to the time at which the current through the secondarycoil reaches zero, current within the circuit flows only through thediodes of the recently-active half-cycle pair, resulting once again in aspike in voltage. Such a voltage spike is referred to herein as a“trailing-edge spike.” The amplitude of this voltage spike is theforward voltage of the rectifier diode and the width is the delay fromthe turn-off of the rectifier switch until the current through thesecondary coil 226 reaches zero.

More specifically, as the current of a positive half-cycle decreasestoward zero, the processor 220 disables the rectifier switches 228 a and228 c. Thereafter, remaining current in the circuit flows through therectifying diodes 230 a and 230 c, resulting in an increase in voltagebecause of the forward voltage exhibited by the diodes. In other words,voltage measured from node a to node b in the illustrated schematic(e.g., across the source and drain of the rectifying switch 228 a)spikes as a result of current flowing through the rectifying diode 230a. A similar voltage spike can be measured across the source and drainof the rectifying switch 228 c.

Similarly, as the current of a negative half-cycle increases towardzero, the processor 220 disables the rectifier switches 228 b and 228 d.Thereafter, current in the circuit flows through the rectifying diodes230 b and 230 d, resulting in a rapid increase in voltage across therectifier switches 228 b and 228 d because of the forward voltageexhibited by the diodes.

More simply, in operation, the voltage across the source and drain ofthe rectifier switches 228 a, 228 b, 228 c, and 228 d, when measuredover a half-period, exhibits a leading edge voltage spike, asubstantially flat conducting period, and a trailing-edge voltage spike,such as depicted in FIG. 3B, which is a waveform representation ofcurrent and voltage measured across the output of the secondary coil 226of the wireless power transfer system 200 of FIG. 2. Depicted in FIG. 3Bare two periods of induced alternating current and alternating voltageprior to rectification by the synchronous rectifier 224: a positivehalf-cycle 308, a negative half-cycle 310, a second positive half-cycle312, and a second negative half-cycle 314. The voltage of eachhalf-cycle exhibits a leading edge voltage spike 316, a substantiallyflat conducting period 318, and a trailing-edge voltage spike 320 thatgenerally begins at time t₁. The substantially flat conducting period318 is illustrated as slightly deformed to represent a slight increasein voltage resulting from internal resistance of the rectifier switches228 a, 228 b, 228 c, and 228 d.

Next, reference is made to the operation of the circuit of the exampleembodiment illustrated in FIG. 2 as it relates to in-band signaling fromthe load device. As noted above with respect to other exampleembodiments, it is appreciated that the operation of the particularillustrated embodiment and schematic diagram is a generalized tofacilitate an understanding of the various embodiments described herein;other circuit topologies can operate in a different manner to affectin-band signaling from the load device to the source device than thatdescribed below.

For many embodiments described herein, digital information istransferrable from the load device 204 to the source device 202 viain-band signaling at a baud rate equivalent to, or a multiple (orfactor) of, the operational frequency of the wireless power transfersystem 200. In general, in these embodiments, the processor 220 of theload device 204 selectively modifies the timing of (e.g., delays) one ormore switches of the synchronous rectifier 224 during a transitionbetween half-cycles, thereby suppressing the trailing-edge voltage spikethat results from the conduction of current by the rectifying diode(s)associated with the switches. This delay allows the induced currentthrough the secondary coil 226 to invert (e.g., change sign), reversingdirection, while the conducting rectifier switch is active. This, inturn, causes power to be reflected to the source device 202.

In another non-limiting phrasing, the baud rate (e.g., the number ofbits sent per second) may be related to the operational frequency of thewireless power transfer system 200 specifically because data iscommunicated from the load device 204 to the source device 202 withinthe same band (e.g., not requiring a separate communication channel andnot requiring high-frequency modulation and subsequent demodulation) asthe power transfer. In one example, a single bit can be transmitted forevery half-cycle of induced voltage; the baud rate may be twice theoperational frequency. In another example, two bits can be transmittedfor every half-cycle (e.g., by modification of the timing by differentamounts) of induced voltage; the baud rate may be four times theoperational frequency. In yet another example, a single bit may betransmitted for every five periods of induced voltage; the baud rate maybe 20 percent of the operational frequency. In yet another example, asingle bit may be transmitted only for the falling edge of inducedvoltage; the baud rate may be equal to the operational frequency. It maybe appreciated that the examples provided above are presented merely tofacilitate an understanding of various embodiments described herein;different encoding schemes, different operational frequencies, differentencryption techniques, different error checking methods, and so on canbe used in different embodiments to achieve different baud rates thatmay be suitable for specific implementations.

Particularly, FIG. 4A is a waveform representation of a singlehalf-cycle 400 of current and voltage associated with the rectifierswitch 228 a during a de-synchronization operation performed by thesynchronous rectifier 224. Depicted in FIG. 4B is a control signal 406that may be applied to the rectifier switch 228 a (e.g., gate voltagesignal) to affect the de-synchronization. The voltage waveform of FIG.4A includes a leading edge voltage spike 402 and a substantially flatconducting period 404, but does not include a trailing-edge voltagespike, as shown for each half-cycle depicted in FIG. 3B. In other words,the rectifier switch 228 a is disabled at a time t₁′ that is later thanthe time t₁ at which the rectifier switches of FIG. 3B are otherwisedisabled, thereby suppressing the trailing-edge voltage spike (labeledas a smooth trailing-edge 408) that would otherwise occur. Thetrailing-edge voltage spike is suppressed because the rectifier diodedoes not conduct current since the current has crossed zero (e.g.,reversed) at the time the rectifier switch is turned off. This delay,shown in FIG. 4B as the delay 410, allows the induced current to brieflycontinue into the opposite half-cycle, reversing direction, and causingpower to be reflected to the source device 202.

In some embodiments, the processor 220 may perform an operation todetermine an optimal delay to implement in order to sufficientlysuppress the trailing-edge voltage spike in a manner that can bedetected by the load device 204. For example, the processor 220 mayprogressively increase the implemented delay until the source device 202confirms that it is able to detect power reflected by the load device204 and to obtain digital information therefrom.

In this manner, by selectively desynchronizing the synchronous rectifier224 on a per half-cycle basis (or a slower rate for some embodiments),the load device 204 can communicate digital information to the sourcedevice 202.

Next, reference is made to the operation of the circuit of the exampleembodiment illustrated in FIG. 2 as it relates to in-band signalreceiving from the source device. As noted above with respect to otherexample embodiments, it is appreciated that the operation of theparticular illustrated embodiment and schematic diagram is a generalizedto facilitate an understanding of the various embodiments describedherein; other circuit topologies can operate in a different manner toaffect in-band signaling from the load device to the source device thanthat described below.

Particularly, the source device 202 detects the presence or absence of areduction in power transfer due to the momentary current reversal andcorresponding power reflection and records the presence as a digitalbit. In one embodiment, the presence or absence of reflected power isbuffered by the source device 202 as a binary bit (e.g., present or notpresent). In other cases, the source device 202 can use, collect, store,forward, or ignore received bits in any other number of suitable ways.For example, the source device 202 can buffer, cache, store, recordedbits until a symbol, instruction, header, checksum, an end-of-messageindication, or other data is received.

For example, FIGS. 5A-5B is a waveform representation of the current andvoltage measured across the output of the inverter 210 of FIG. 200.Depicted are periods of alternating current: a first positive half-cycle500, a first negative half-cycle 503, a second positive half-cycle 504,and a second negative half-cycle 506. The depicted waveform alsoincludes a current zero-crossing 508 immediately before the transitionbetween the first positive half-cycle 500 and the first negativehalf-cycle 502. This current reversal is detectable by the processor 206of the source device 202, and can be interpreted as a digital bit 510such as shown in FIG. 5B. The current zero-crossing 508 can be anysuitable current reversal (or, in some embodiments, currenttransitioning through a threshold) that is detectable by the processor206.

In some embodiments that utilize dead-time control for inverter switchesof an inverter of a source device, the associated inverter diodes (suchas the inverter diodes 214 a and 214 d or 214 b and 214 c as shown inFIG. 2) may carry the current within the primary coil during thedead-time interval. In embodiments where active switches are turned offprior to the current within the primary coil reaching zero, the inverterdiodes associated with the inactive switch pair will conduct until thecurrent reaches zero.

As an example, reference is made to the embodiment depicted in FIG. 2.In this case, if the inverter switches 212 a and 212 d are turned offprior to zero current carried therethrough, then the inverter diodes 214b and 214 c will conduct until the current reaches zero or until theinverter switches 212 b and 212 c are turned on. In this case, aleading-edge voltage spike 520 associated with the inverter diodeconduction appears at the switches as depicted in FIG. 5A.

In the case where the current changes sign prior to the time when theactive inverter switches are turned off, the inverter diodes associatedwith the recently active switch will conduct to carry the windingcurrent until the opposite switch phase is turned on. In this case atrailing-edge voltage spike 522 associated with the inverter diodeconduction would appear at the inverter switches, such as depicted inFIG. 5A. As an example, if the inverter switches 212 a and 212 d of FIG.2 are turned off after the current changes sign then inverter diodes 214a and 214 d will conduct until the inverter switches 212 b and 212 c areturned on.

At the time the inverter switches 212 b and 212 c are turned on (whilethe inverter diodes 214 a and 214 d are conducting) there may be a briefinterval of reverse recovery shoot-through current carried until theassociated inverter diodes turn off. The peak current and associatedpower loss associated with this shoot-though is, in many examples,dependent on the reverse recovery time of the inverter diodes. Thisreverse recovery shoot-through can also occur on the opposite invertercycle when the inverter switches 212 a and 212 d are turned on (whilethe inverter diodes 214 b and 214 c are conducting) until the associatedinverter diodes turn off. Some embodiments may utilize separatehigh-speed Schottky inverter diodes to minimize the peak current andlosses associated with the reverse recovery time, thereby preventingsaid current from causing damage to one or more of the inverter switches212 a, 212 b, 212 c, and 212 d.

In some embodiments, the digital bit 510 may be set at the moment thetrailing-edge voltage spike 522 is detected by the processor 206 at thecompletion of half-cycle 500. Conversely, another digital bit 512,having a different value than the digital bit 510, is set at thehalf-cycle 502 completes without experiencing a trailing-edge voltagepulse. Similarly, another digital bit 514, having a different value thanthe digital bit 510, may be set at the moment the second positivehalf-cycle 504 completes without experiencing a trailing-edge voltagepulse. Similarly, another digital bit 516, having a different value thanthe digital bit 510, is set at the moment the second negative half-cycle506 completes without experiencing a trailing-edge voltage pulse. Inthis manner, through two periods of alternating current (e.g., invertercycles), the load device 204 communicates four bits of information tothe source device 202. For example, in the illustrated embodiment, thebinary information communicated from the load device 204 to the sourcedevice 202 can be a binary representation of the number eight, (1000)₂.

In one example, the processor 206 of the source device 202 monitors forchanges in current through one or more of the inverter switches 212 a,212 b, 212 c, and 212 d of the inverter 210. Particularly, when areduction in power transferred occurs, current through one or more ofthe inverter switches 212 a, 212 b, 212 c, and 212 d is reduced. Theprocessor 206 can monitor for this reduction by determining whether thecurrent through an inverter switch is lower than a selected threshold.In other cases, the processor 206 can monitor a voltage across anelement of known resistance.

In other cases, the processor 206 of the source device 202 can monitorthe current over time through one or more of the inverter switches 212a, 212 b, 212 c, and 212 d for a phase shift and record the phase shiftas a binary bit. In other cases, the source device 202 can monitor themagnitude of the reduction in power transferred (e.g., currentmonitoring, voltage monitoring, phase shift monitoring, and so on) andcan quantize the same into one or more non-binary values.

Alternatively, should the source device 202 detect the absence of anyreduction in power transferred, the source device 202 buffers theabsence of reduction in power transferred as a complementary digitalbit. The source device buffers recorded bits until a symbol,instruction, header, or other data is received. For example, FIG. 6Adepicts a waveform representation of voltage output from the synchronousrectifier 224 of FIG. 2, illustrating in-band signaling viatrailing-edge voltage spike suppression. Illustrated are eighthalf-cycles, showing three suppressed trailing edge spikes, 600, 602,and 604. As with other embodiments described herein, the processor 206of the source device 202 can monitor for the reductions in powertransferred associated with the three suppressed trailing edge spikes,600, 602, and 604 and can interpret said reductions in power transferredas a digital bits such as shown in FIG. 6B. In the embodiment depictedin FIG. 6B, the binary information communicated from the load device 204to the source device 202 can be a binary representation of the number162, (1010 0010)₂. In some cases, the processor 206 interprets thepresence of a reduction in power transferred as an asserted binary bit(e.g., 1) and the absence of a reduction in power transferred as a nullbinary bit (e.g., 0). In other cases, the processor 206 interprets theabsence of a reduction in power transferred as an asserted binary bitand the presence of the reduction in power transferred as a null binarybit. In further embodiments, the coding scheme of the in-band signalingbetween the load device 204 and the source device 202 can changedepending upon the power requirements of the load device 204.

In this manner, digital information is transferrable from a load deviceto a source device via in-band signaling at a baud rate equivalent to,or a multiple or factor of, the operational frequency of the wirelesspower transfer system. As noted above, a load device selectivelymodifies the timing of (e.g., delays, phase shifts, and so on) arectifier within the load device during a transition from a onehalf-cycle to the other half-cycle, thereby causing a reduction in thepower transferred from the source device to the load device.

A more general representation of wireless power transfer systemembodiments configured for in-band communication from the load device toa source device are depicted in FIGS. 7A-7B. FIG. 7A is a simplifiedsystem diagram of a load device 702 of a wireless power transfer systemfacilitating in-band signaling. The load device 702 includes a processor704 to perform, monitor, and/or coordinate the operations of the loaddevice 702. The processor 704 is coupled to a variable load 706 whichitself is coupled to a rectifier 708 that receives alternating currentfrom a receive coil 710. The receive coil 710 receives power from asource device. The rectifier 708 is controlled, at least partially, by atiming adjuster 714. The timing adjuster 714 responds to a data signalfrom the processor 704 to selectively modify the timing (e.g., turn-off,turn-on) of one or more switches 712 of the rectifier 708. In somecases, the timing adjuster 714 is a portion of the processor 704, inother cases, the timing adjuster 714 is implemented as a separatecircuit and/or processor. In some cases, the delay (or phase shift)provided by the timing adjuster 714 is configurable by the processor704.

FIG. 7B is a simplified system diagram of a source device 716 of awireless power transfer system facilitating in-band signaling. Thesource device 716 includes a processor 718 coupled to a power source720. The power source 720 supplies power to a bridge inverter 722 thatoutputs alternating current to a transmit coil 724. The bridge inverter722 also includes a monitor 728 that is configured to monitor themagnitude and/or phase of current or voltage of one or more switches 726of the bridge inverter 722.

FIG. 8 depicts operations of a method of in-band signaling from a loaddevice to a source device of a wireless power transfer system. Themethod begins at operation 800 in which a load device determinesinformation (e.g., a data signal) that the load device desires tocommunicate to a source device over a wireless power transfer interface.The information communicated from the load device to the source devicecan be any suitable information. For example, the load device cancommunicate that a battery within the load device is fully charged. Theload device can communicate that the load device is in need or morepower. The load device can communicate a temperature of the load device.The load device can communicate authentication information to the sourcedevice. It is appreciated that the above are merely examples; a loaddevice can communicate any suitable or implementation-specificinformation to a source device in different embodiments.

Next at operation 802, the load device causes a delay (and/or phaseshift) in the gate voltage turn-off of one switch of a rectifier duringa particular rectification cycle. The delay causes a reduction in powertransferred across the wireless power transfer interface.

FIG. 9 depicts operations of a method of demodulating an in-band signalfrom a load device to a source device of a wireless power transfersystem. The method begins at operation 900 in which a source devicemonitors current through one or more switches of an inverter bridge. Thesource device monitors for a current reversal (or, more generally, acurrent threshold crossing) that is associated with a reduction in powertransferred from a load device. If a current reversal is detected atoperation 902, then a first bit value is buffered within the sourcedevice at operation 904. Alternatively, if a current reversal is notdetected at operation 902, then a second bit value is buffered withinthe source device at operation 906. Bits may be buffered until a patternof bits is received. Thereafter, the pattern can be interpreted by aprocessor as data received from the load device.

FIG. 10 depicts operations of a method of demodulating an in-band signalfrom a load device to a source device of a wireless power transfersystem. The method begins at operation 1000 in which a source devicemonitors the phase of current through a transmit coil within the sourcedevice. The source device monitors for a phase shift that is associatedwith a reduction in power transferred to a load device. If a phase shiftis detected at operation 1002, then a first bit value is buffered withinthe source device at operation 1004. Alternatively, if a phase shift isnot detected at operation 1002, then a second bit value is bufferedwithin the source device at operation 1006.

FIG. 11 depicts operations of a method of demodulating an in-band signalfrom a load device to a source device of a wireless power transfersystem. The method begins at operation 1100 in which a source devicemonitors for a trailing edge voltage spike at a transmit coil within thesource device. The source device monitors for a for a trailing edgevoltage spike that is associated with diode conduction due to currentreversal due to timing modifications in the load device. If a for atrailing edge voltage spike is detected at operation 1102, then a firstbit value is buffered within the source device at operation 1104.Alternatively, if a for a trailing edge voltage spike is not detected atoperation 1102, then a second bit value is buffered within the sourcedevice at operation 1106.

FIG. 12 depicts operations of a method of adjusting the data transferrate of in-band signaling from a load device to a source device of awireless power transfer system. The method begins at operation 1200 atwhich a high error rate in an in-band signaling channel is detected by asource device. The high error rate can be detected by any suitable errordetection means.

If a high error rate is detected, the method continues to operation 1202in which a current threshold for current reversal and/or phase shiftdefining a reduction in power transferred are either increased ordecreased. If the error rate continues to increase, the threshold can bechanged in the opposite direction. Once a minimum error rate isestablished, the source device can save the threshold value in a memoryfor future use.

One may appreciate that although many embodiments are disclosed above,that the operations and steps presented with respect to methods andtechniques described herein are meant as exemplary and accordingly arenot exhaustive. One may further appreciate that alternate step order or,fewer or additional steps may be required or desired for particularembodiments.

Although the disclosure above is described in terms of various exemplaryembodiments and implementations, it should be understood that thevarious features, aspects and functionality described in one or more ofthe individual embodiments are not limited in their applicability to theparticular embodiment with which they are described, but instead can beapplied, alone or in various combinations, to one or more of the someembodiments of the invention, whether or not such embodiments aredescribed and whether or not such features are presented as being a partof a described embodiment. Thus, the breadth and scope of the presentinvention should not be limited by any of the above-described exemplaryembodiments but is instead defined by the claims herein presented.

1. (canceled)
 2. A method of transmitting data from a load device to asource device in a wireless power transfer system, the methodcomprising: determining, by the load device, an update to becommunicated from the load device to the source device as a data signal;wirelessly transferring power from the source device to the load device;and desynchronizing, by the load device, a timing of a rectifier in theload device according to a pattern corresponding to the data signal. 3.The method of claim 2, wherein: the rectifier comprises a switch; andmodifying the timing of the rectifier comprises delaying a turn off theswitch.
 4. The method of claim 3, wherein delaying the turn off of theswitch comprises delaying a turn off until current through the switchreverses.
 5. The method of claim 3, wherein delaying the turn off of theswitch suppress a voltage spike associated with current conductionthrough a diode within the load device.
 6. The method of claim 5,wherein the diode is one of: a body diode of the switch; or a Schottkydiode coupled across a source and a drain of the switch.
 7. The methodof claim 2, wherein the update comprises an indication that a batterywithin the load device is charged.
 8. The method of claim 2, wherein theupdate comprises authentication information.
 9. The method of claim 2,wherein the update comprises executable instructions received by aprocessor of the source device.
 10. The method of claim 2, wherein theupdate comprises temperature information corresponding to a temperatureof the load device.
 11. A method for updating a source device from aload device in a wireless power transfer system, the method comprising:receiving, by the load device, an update to be communicated from theload device to the source device as a data signal; wirelesslytransmitting power from the source device to the load device;desynchronizing, by the load device, a rectifier of the load devicebased on the digital signal; determining, by the source device, that acurrent threshold crossing has occurred within an electronic element ofthe source device; recording, by the source device, a digital bit basedon the current threshold crossing; and buffering, by the source device,the digital bit as a portion of the data signal.
 12. The method of claim11, wherein; the source device comprises an inverter; and the operationof determining that the current threshold crossing has occurredcomprises monitoring a switch of the inverter for a threshold crossingin current.
 13. The method of claim 11, wherein the update comprises atemperature of the load device.
 14. The method of claim 11, wherein theupdate comprises executable instructions for a processor of the sourcedevice.
 15. A wireless power transfer system, comprising: a sourcedevice comprising: an inverter; a transmit coil coupled to the inverter;and a first processor configured to monitor current in the inverter; anda load device comprising: a receive coil magnetically coupled to thetransmit coil; a rectifier coupled to the receive coil and comprising aswitch; and a second processor coupled to the switch and configured to:determine an executable instruction to be communicated from the loaddevice to the source device as a data signal; and delay of a turn off ofthe switch based on the data signal.
 16. The wireless power transfersystem of claim 15, wherein the first processor is configured to: recorda first digital bit to a buffer in response to the monitored currentcrossing a threshold; and record a second digital bit to the buffer inresponse to the monitored current not crossing the threshold.
 17. Thewireless power transfer system of claim 16, wherein the threshold isassociated with a trailing edge voltage spike within the inverter. 18.The wireless power transfer system of claim 16, wherein the threshold isassociated with a leading edge voltage spike within the inverter. 19.The wireless power transfer system of claim 15, wherein the firstprocessor is configured to: record a first digital bit to a buffer inresponse to the monitored current shifting phase; and record a seconddigital bit to the buffer in response to the monitored current notshifting phase.
 20. The wireless power transfer system of claim 15,wherein the first processor is configured to receive and execute theexecutable instruction.
 21. The wireless power transfer system of claim15, wherein the load device is a portable electronic device.